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ADVANCE INFORMATION
WORD-WIDE FlashFileTM MEMORY FAMILY 28F160S3, 28F320S3
Includes Extended Temperature Specifications
Two 32-Byte Write Buffers 2.7 s per Byte Effective Programming Time Low Voltage Operation 2.7V or 3.3V VCC 2.7V, 3.3V or 5V V PP 100 ns Read Access Time (16 Mbit) 110 ns Read Access Time (32 Mbit) High-Density Symmetrically-Blocked Architecture 32 64-Kbyte Erase Blocks (16 Mbit) 64 64-Kbyte Erase Blocks (32 Mbit) System Performance Enhancements STS Status Output Industry-Standard Packaging BGA* package, SSOP, and TSOP (16 Mbit) BGA* package and SSOP (32 Mbit)
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Cross-Compatible Command Support Intel Standard Command Set Common Flash Interface (CFI) Scaleable Command Set (SCS) 100,000 Block Erase Cycles Enhanced Data Protection Features Absolute Protection with V PP = GND Flexible Block Locking Block Erase/Program Lockout during Power Transitions Configurable x8 or x16 I/O Automation Suspend Options Program Suspend to Read Block Erase Suspend to Program Block Erase Suspend to Read ETOXTM V Nonvolatile Flash Technology
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Intel's Word-Wide FlashFileTM memory family provides high-density, low-cost, non-volatile, read/write storage solutions for a wide range of applications. The Word-Wide FlashFile memories are available at various densities in the same package type. Their symmetrically-blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the Word-Wide FlashFile memories offer three levels of protection: absolute protection with VPP at GND, selective block locking, and program/erase lockout during power transitions. These alternatives give designers ultimate control of their code security needs. This family of products is manufactured on Intel's 0.4 m ETOXTM V process technology. It comes in the industry-standard 56-lead SSOP and BGA packages. In addition, the 16-Mb device is available in the industry-standard 56-lead TSOP package.
June 1997
Order Number: 290608-001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F160S3 and 28F320S3 may contain design defects or errors known as errata. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel's website at http:\\www.intel.com
COPYRIGHT (c) INTEL CORPORATION, 1997 CG-041493
*Third-party brands and names are the property of their respective owners.
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CONTENTS
PAGE PAGE 4.9 Byte/Word Write Command ........................27 4.10 STS Configuration Command...................28 4.11 Block Erase Suspend Command ..............28 4.12 Program Suspend Command ...................28 4.13 Set Block Lock-Bit Commands .................29 4.14 Clear Block Lock-Bits Command ..............29 5.0 DESIGN CONSIDERATIONS ........................39 5.1 Three-Line Output Control..........................39 5.2 STS and WSM Polling ................................39 5.3 Power Supply Decoupling ..........................39 5.4 VPP Trace on Printed Circuit Boards...........39 5.5 VCC, VPP, RP# Transitions..........................39 5.6 Power-Up/Down Protection ........................39 6.0 ELECTRICAL SPECIFICATIONS..................40 6.1 Absolute Maximum Ratings ........................40 6.2 Operating Conditions..................................40 6.2.1 Capacitance.........................................41 6.2.2 AC Input/Output Test Conditions .........41 6.2.3 DC Characteristics...............................42 6.2.4 AC Characteristics - Read-Only Operations..........................................44 6.2.5 AC Characteristics - Write Operations .46 6.2.6 Reset Operations.................................48 6.2.7 Erase, Program, And Lock-Bit Configuration Performance.................49 APPENDIX A: Device Nomenclature and Ordering Information ..................................51 APPENDIX B: Additional Information ...............52
1.0 INTRODUCTION .............................................5 1.1 New Features...............................................5 1.2 Product Overview.........................................5 1.3 Pinout and Pin Description ...........................6 2.0 PRINCIPLES OF OPERATION .....................10 2.1 Data Protection ..........................................11 3.0 BUS OPERATION .........................................12 3.1 Read ..........................................................12 3.2 Output Disable ...........................................12 3.3 Standby......................................................12 3.4 Deep Power-Down .....................................12 3.5 Read Query Operation ...............................12 3.6 Read Identifier Codes Operation ................13 3.7 Write ..........................................................13 4.0 COMMAND DEFINITIONS ............................13 4.1 Read Array Command................................16 4.2 Read Query Mode Command.....................17 4.2.1 Query Structure Output .......................17 4.2.2 Query Structure Overview ...................19 4.2.3 Block Status Register ..........................20 4.2.4 CFI Query Identification String.............21 4.2.5 System Interface Information...............22 4.2.6 Device Geometry Definition .................23 4.2.7 Intel-Specific Extended Query Table ...24 4.3 Read Identifier Codes Command ...............25 4.4 Read Status Register Command................25 4.5 Clear Status Register Command................26 4.6 Block Erase Command ..............................26 4.7 Full Chip Erase Command .........................26 4.8 Write to Buffer Command...........................27
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REVISION HISTORY
Description Original version
Number -001
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1.0 1.1
* * * *
28F160S3, 28F320S3
This family of products are optimized for fast factory programming and low power designs. Specifically designed for 3V systems, the 28F160S3 and 28F320S3 support read operations at 2.7V-3.6V Vcc with block erase and program operations at 2.7V-3.6V and 5V VPP. High programming performance is achieved through highly-optimized write buffers. A 5V VPP option is available for even faster factory programming. For a simple low power design, VCC and VPP can be tied to 2.7V. Additionally, the dedicated VPP pin gives complete data protection when VPP VPPLK. Internal VPP detection configures the device operations. circuitry automatically for optimized write
INTRODUCTION
This datasheet contains 16- and 32-Mbit WordWide FlashFileTM memory (28F160S3 and 28F320S3) specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications for extended temperature product offerings.
New Features
The Word-Wide FlashFile memory family maintains basic compatibility with Intel's 28F016SA and 28F016SV. Key enhancements include: Common Flash Interface (CFI) Support Scaleable Command Set (SCS) Support Low Voltage Technology Enhanced Suspend Capabilities
They share a compatible Status Register, basic software commands, and pinout. These similarities enable a clean migration from the 28F016SA or 28F016SV. When upgrading, it is important to note the following differences: * Because of new feature and density options, the devices have different manufacturer and device identifier codes. This allows for software optimization. New software commands. To take advantage of low voltage on the 28F160S3 and 28F320S3, allow VPP connection to VCC. The 28F160S3 and 28F320S3 do not support a 12V VPP option.
A Common Flash Interface (CFI) permits OEMspecified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scaleable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal device operation. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device's 64-Kbyte blocks typically within tWHQV2/EHQV2 independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Data is programmed in byte, word or page increments. Program suspend mode enables the system to read data or execute code from any other flash memory array location. 5
* *
1.2
Product Overview
The Word-Wide FlashFile memory family provides density upgrades with pinout compatibility for the 16- and 32-Mbit densities. They are highperformance memories arranged as 1 Mword and 2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of 8 bits. This data is grouped in thirty-two and sixtyfour 64-Kbyte blocks that can be erased, locked and unlocked in-system. Figure 1 shows the block diagram, and Figure 5 illustrates the memory organization.
ADVANCE INFORMATION
28F160S3, 28F320S3
The device incorporates two Write Buffers of 32 bytes (16 words) to allow optimum-performance data programming. This feature can improve system program performance by up to four times over non-buffer programming. Individual block locking uses a combination of block lock-bits to lock and unlock blocks. Block lock-bits gate block erase, full chip erase, program and write to buffer operations. Lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits commands) set and clear lock-bits. The Status Register and the STS pin in RY/BY# mode indicate whether or not the device is busy executing an operation or ready for a new command. Polling the Status Register, system software retrieves WSM feedback. STS in RY/BY# mode gives an additional indicator of WSM activity by providing a hardware status signal. Like the Status Register, RY/BY#-low indicates that the WSM is performing a block erase, program, or lockbit operation. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and program is inactive), program is suspended, or the device is in deep power-down mode.
The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit mode with address A0 selecting between the low byte and high byte. BYTE# at logic high enables 16-bit operation with address A1 becoming the lowest order address. Address A0 is not used in 16bit mode. When one of the CEX# pins (CE0#, CE1#) and RP# pins are at VCC, the component enters a CMOS standby mode. Driving RP# to GND enables a deep power-down mode which significantly reduces power consumption, provides write protection, resets the device, and clears the Status Register. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized.
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1.3
Pinout and Pin Description
The 16-Mbit device is available in the 56-lead TSOP, 56-lead SSOP and BGA packages. The 32- Mb device is available in the 56-lead SSOP and BGA packages. The pinouts are shown in Figures 2, 3 and 4.
DQ0 - DQ15
Output Buffer
Input Buffer
Query Output Multiplexer Write Buffer Data Register Identifier Register Status Register
I/O Logic
VCC BYTE# CE# WE# OE# RP# WP#
Command User Interface
Multiplexer Data Comparator
16-Mbit: A0- A20 32-Mbit: A0 - A21
Y-Decoder Input Buffer
Y-Gating Write State Machine 16-Mbit: Thirty-two 32-Mbit: Sixty-four 64-Kbyte Blocks Program/Erase Voltage Switch
STS VPP VCC GND
Address Latch Address Counter
X-Decoder
Figure 1. Block Diagram 6
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Table 1. Pin Descriptions Sym A0-A21 Type INPUT Name and Function 16-Mbit A0-A20 DQ0- DQ15 32-Mbit A0-A21 CE0#, CE1# INPUT RP# INPUT
28F160S3, 28F320S3
ADDRESS INPUTS: Address inputs for read and write operations are internally latched during a write cycle. A 0 selects high or low byte when operating in x8 mode. In x16 mode, A0 is not used; input buffer is off.
INPUT/ DATA INPUTS/OUTPUTS: Inputs data and commands during CUI write cycles; OUTPUT outputs data during memory array, Status Register, query and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders, and sense amplifiers. With CE 0# or CE1# high, the device is deselected and power consumption reduces to standby levels. Both CE 0# and CE1# must be low to select the device. Device selection occurs with the latter falling edge of CE 0# or CE1#. The first rising edge of CE0# or CE1# disables the device. RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations which provides data protection during system power transitions, puts the device in deep power-down mode, and resets internal automation. RP#-high enables normal operation. Exit from deep power-down sets the device to read array mode. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse.
OE# WE# STS
INPUT INPUT
STATUS: Indicates the status of the internal state machine. When configured in OPEN DRAIN level mode (default), it acts as a RY/BY# pin. For this and alternate configurations OUTPUT of the STATUS pin, see the Configuration command. Tie STS to VCC with a pull-up resistor. INPUT INPUT WRITE PROTECT: Master control for block locking. When V IL, locked blocks cannot be erased or programmed, and block lock-bits cannot be set or cleared. BYTE ENABLE: Configures x8 mode (low) or x16 mode (high).
WP# BYTE# VPP
SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY: Necessary voltage to perform block erase, program, and lock-bit configuration operations. Do not float any power pins. SUPPLY DEVICE POWER SUPPLY: Do not float any power pins. Do not attempt block erase, program, or block-lock configuration with invalid VCC values. SUPPLY GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated.
VCC GND NC
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28F160S3 28F160S5 28F016SA 28F016SV
28F016SA 28F160S3 28F016SV 28F160S5
3/5# CE1# NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0# VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
NC CE1# NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0# VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56-LEAD TSOP STANDARD PINOUT 14 mm x 20 mm TOP VIEW
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
WP# WP# WE# WE# OE# OE# RY/BY# STS RY/BY# DQ15 DQ15 DQ7 DQ7 DQ14 DQ14 DQ6 DQ6 GND GND DQ13 DQ13 DQ5 DQ5 DQ12 DQ12 DQ4 DQ4 VCC VCC GND GND DQ11 DQ11 DQ3 DQ3 DQ10 DQ10 DQ2 DQ2 VCC VCC DQ9 DQ9 DQ1 DQ1 DQ8 DQ8 DQ0 DQ0 A0 A0 BYTE# BYTE# NC NC NC NC
Highlights pinout changes.
Figure 2. TSOP 56-Lead Pinout
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Figure 3. SSOP 56-Lead Pinout
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VCC A14 CE0 VPP A10 GND A19 A17 A15 A12 A11 A20 A21 A16 A13 RP# NC CE1 A18 A9 A8 A3 A7 A6 A1 A4 A5 A2 A11 A12 A15 A17 A19 RP# A13 A16 A21 A20 A18 CE1 NC DQ7 WP# WE# WE# WP# DQ7 BYTE# NC NC A0
GND A10 VPP CE0 A14 VCC A4 A5 A2 A7 A6 A1 A9 A8 A3
NC A0
NC BYTE#
DQ8 DQ1 DQ3 DQ12 DQ6 DQ15 OE#
OE# DQ15 DQ6 DQ12 DQ3 DQ1 DQ8
DQ0 DQ9 DQ2 DQ11 DQ4 DQ13 DQ14 STS VCC DQ10 GND VCC DQ5 GND
STS DQ14 DQ13 DQ4 DQ11 DQ2 DQ9 DQ0 GND DQ5 VCC GND DQ10 VCC
Bottom View
This is the view of the package as surface mounted on the board. Note that the signals are mirror imaged.
NOTES: 1. Figures are not drawn to scale. 2. Address A21 is not included in the 28F160S3. 3. More information on BGA* packages is available by contacting your Intel/Distribution sales office.
Figure 4. BGA* Package Pinout
2.0
PRINCIPLES OF OPERATION
The word-wide memories include an on-chip Write State Machine (WSM) to manage block erase, program, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, programming, lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power-down mode (see Bus Operations), the 10
device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Read Array, Status Register, query, and identifier codes can be accessed through the CUI independent of the VPP voltage. Proper programming voltage on VPP enables successful block erasure, program, and lock-bit configuration. All functions associated with altering memory contents--block erase, program, lock-bit configuration--are accessed via the CUI and verified through the Status Register.
ADVANCE INFORMATION
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28F160S3, 28F320S3
Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM that controls the block erase, programming, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, identifier codes, or Status Register data. Interface software that initiates and polls progress of block erase, programming, and lockbit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Program suspend allows system software to suspend a program to read data from any other flash memory array location.
2.1
Data Protection
Depending on the application, the system designer may choose to make the VPP power supply switchable or hardwired to VPPH1/2. The device supports either design practice, and encourages optimization of the processormemory interface. When VPP VPPLK, memory contents cannot be altered. When high voltage is applied to VPP, the two-step block erase, program, or lock-bit configuration command sequences provide protection from unwanted operations. All write functions are disabled when VCC voltage is below the write lockout voltage VLKO or when RP# is at VIL. The device's block locking capability provides additional protection from inadvertent code or data alteration.
Figure 5. Memory Map
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3.0
BUS OPERATION
3.4
Deep Power-Down
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The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
RP# at VIL initiates the deep power-down mode. In read mode, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. RP# must be held low for time tPLPH. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the Status Register is set to 80H. During block erase, programming, or lock-bit configuration modes, RP#-low will abort the operation. STS in RY/BY# mode remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after programming or partially altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. It is important in any automated system to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, programming, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel's Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.1
Read
Block information, query information, identifier codes and Status Registers can be read independent of the VPP voltage. The first task is to place the device into the desired read mode by writing the appropriate read-mode command (Read Array, Query, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Control pins dictate the data flow in and out of the component. CE0#, CE1# and OE# must be driven active to obtain data at the outputs. CE0# and CE1# are the device selection controls, and, when both are active, enable the selected memory device. OE# is the data output (DQ0- DQ15) control: When active it drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH. Figure 17 illustrates a read cycle.
3.2
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ15 are placed in a high-impedance state.
3.3
Standby 3.5 Read Query Operation
CE0# or CE1# at a logic-high level (VIH) places the device in standby mode, substantially reducing device power consumption. DQ0-DQ15 (or DQ0- DQ7 in x8 mode) outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, programming, or lock-bit configuration, the device continues functioning and consuming active power until the operation completes.
The read query operation outputs block status, Common Flash Interface (CFI) ID string, system interface, device geometry, and Intel-specific extended query information.
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3.6
28F160S3, 28F320S3
Read Identifier Codes Operation
3.7
Write
The read-identifier codes operation outputs the manufacturer code, device code, and block lock configuration codes for each block configuration (see Figure 6). Using the manufacturer and device codes, the system software can automatically match the device with its proper algorithms. The block-lock configuration codes identify each block's lock-bit setting.
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the Status Register. Additionally, when VPP = VPPH1/2, block erasure, programming, and lock-bit configuration can also be performed. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Write command requires the command and address of the location to be written. Set Block Lock-Bit commands require the command and address within the block to be locked. The Clear Block Lock-Bits command requires the command and an address within the device. The CUI does not occupy an addressable memory location. It is written when WE#, CE0#, and CE1# are active and OE# = VIH. The address and data needed to execute a command are latched on the rising edge of WE# or CEX# (CE0#, CE1#), whichever goes high first. Standard microprocessor write timings are used. Figure 18 illustrates a write operation.
4.0
COMMAND DEFINITIONS
VPP voltage VPPLK enables read operations from the Status Register, identifier codes, or memory blocks. Placing VPPH1/2 on VPP enables successful block erase, programming, and lockbit configuration operations. Device operations are selected by writing specific commands into the CUI. and Table 3 define these commands. Figure 6. Device Identifier Code Memory Map
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Table 2. Bus Operations RP# VIH VIH VIH CE0# VIL VIL VIL VIH VIH CE1# OE#(11) WE#(11) VIL VIL VIH VIL VIH X VIL VIL VIL X VIL VIL VIH X VIH VIH VIL X See Figure 6 See Table 6 X X X X VPPH1/2 High Z High Z(9) DOUT DOUT DIN High Z(9) High Z(9) X VIL VIH X VIH VIH X Address X X X VPP X X X DQ(8) DOUT High Z High Z STS(3) X X X VIL VIH VIH VIH X VIL VIL VIL
Mode Read Output Disable Standby
Notes 1,2
Reset/PowerDown Mode Read Identifier Codes Read Query Write
NOTES:
10 4 5 3,6,7
1. Refer to Table 19. When VPP VPPLK, memory contents can be read, but not altered. 2. X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP. See Table 19, for VPPLK and VPPH1/2 voltages. 3. STS in level RY/BY# mode (default) is VOL when the WSM is executing internal block erase, programming, or lock-bit configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or deep power-down mode. 4. See Section 4.3 for read identifier code data. 5. See Section 4.2 for read query data. 6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when V = VPPH1/2 and PP VCC = VCC1/2 (see Section 6.2). 7. Refer to Table 3 for valid DIN during a write operation. 8. DQ refers to DQ0-7 if BYTE# is low and DQ0-15 if BYTE# is high. 9. High Z will be VOH with an external pull-up resistor. 10. RP# at GND 0.2V ensures the lowest deep power-down current. 11. OE# = VIL and WE# = VIL concurrently is an undefined state and should not be attempted.
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Command Scaleable Bus Notes or Basic Cycles Command Req'd Set(14) First Bus Cycle Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Write to Buffer Word/Byte Program SCS/BCS SCS/BCS SCS SCS/BCS SCS/BCS SCS SCS/BCS 1 2 2 2 1 >2 2 8, 9, 10 6,7 5 Write Write Write Write Write Write Write X X X X X BA X FFH 90H 98H 70H 50H E8H 40H or 10H 20H B0H D0H B8H 60H 60H 30H
28F160S3, 28F320S3
Table 3. Word-Wide FlashFileTM Memory Command Set Definitions(13) Second Bus Cycle
Oper(1) Addr(2) Data(3,4) Oper(1) Addr(2) Data(3,4)
Read Read Read
IA QA X
ID QD SRD
Write Write
BA PA
N PD
Block Erase
SCS/BCS
2 1 1 2 2 2 2
6,10 6 6
Write Write Write Write
X X X X X X X
Write
BA
D0H
Block Erase, Word/Byte SCS/BCS Program Suspend Block Erase, Word/Byte SCS/BCS Program Resume STS pin Configuration Set Block Lock-Bit Clear Block Lock-Bits Full Chip Erase SCS SCS SCS SCS
Write Write Write Write
X BA X X
CC 01H D0H D0H
11 12 10
Write Write Write
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NOTES: 1. Bus operations are defined in Table 2. 2. X = Any valid address within the device. BA = Address within the block being erased or locked. IA = Identifier Code Address: see Table 12. QA = Query database Address. PA = Address of memory location to be programmed. 3. ID = Data read from Query database. SRD = Data read from Status Register. See Table 15 for a description of the Status Register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#. CC = Configuration Code. (See Table 14.) 4. The upper byte of the data bus (DQ8-15) during command writes is a "Don't Care" in x16 operation.
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5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See Section 4.3 for read identifier code data. 6. If a block is locked (i.e., the block's lock-bit is set to 0), WP# must be at VIH in order to perform block erase, program and suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is V IL will fail. 7. Either 40H or 10H are recognized by the WSM as the byte/word program setup. 8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available. 9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1 byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the buffer boundary causes unexpected results and should be avoided. 10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued. Confirm also reactivates suspended operations. 11. A block lock-bit can be set only while WP# is VIH. 12. WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. 13. Commands other than those shown above are reserved for future use and should not be used. 14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
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4.1 4.2
28F160S3, 28F320S3
Query data are always presented on the lowestorder data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this device, the Query table device starting address is a 10h word address, since the maximum bus width is x16. For this word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). Since the device is x8/x16 capable, the x8 data is still presented in word-relative (16-bit) addresses. However, the "fill data" (00h) is not the same as driven by the upper bytes in the x16 mode. As in x16 mode, the byte address (A0) is ignored for Query output so that the "odd byte address" (A0 high) repeats the "even byte address" data (A0 low). Therefore, in x8 mode using byte addressing, the device will output the sequence "Q", "Q", "R", "R", "Y", "Y", and so on, beginning at byte-relative address 20h (which is equivalent to word offset 10h in x16 mode). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address.
Read Array Command
Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started block erase, program, or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation--unless the WSM is suspended via an Erase-Suspend or ProgramSuspend command. The Read Array command functions independently of the VPP voltage.
Read Query Mode Command
This section defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI. 4.2.1 QUERY STRUCTURE OUTPUT
The Query "database" allows system software to gain critical information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data.
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28F160S3, 28F320S3
Table 4. Summary of Query Structure Output as a Function of Device and Mode Device Type/Mode Word Addressing Location x16 device/ x16 mode x16 device/ x8 mode 10h 11h 12h N/A(1) Query Data Hex, ASCII 0051h "Q" 0052h "R" 0059h "Y" N/A 20h 21h 22h 20h 21h 22h Byte Addressing Location
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"Q" null "R" "Q" "Q" "R"
Query Data Hex, ASCII 51h 00h 52h 51h 51h 52h
NOTE: 1. The system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. Therefore, word addressing where lower addresses are not toggled by the system is"Not Applicable" for x8configured devices.
Table 5. Example of Query Structure Output of a x16- and x8-Capable Device Device Address A16-A1 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051h 0052h 0059h P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Word Addressing: Query Data D15-D0 "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # Byte Address A7-A0 20h 21h 22h 23h 24h 25h 26h 27h 28h ... 51h 51h 52h 52h 59h 59h P_IDLO P_IDLO P_IDHI ... Byte Addressing: Query Data D7-D0 "Q" "Q" "R" "R" "Y" "Y" PrVendor ID #
"
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4.2.2 QUERY STRUCTURE OVERVIEW The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized in Table 8. The following sections describe the Query structure sub-sections in detail. Table 6. Query Structure(1) Offset 00h 01h (BA+2)h(2) 04-0Fh 10h 1Bh 27h P(3) Block Status Register Sub-Section Name Manufacturer Code Device Code
28F160S3, 28F320S3
Description
Block-specific information
Reserved
CFI Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table
Reserved for vendor-specific information
Command set ID and vendor data offset Device timing & voltage information Flash device layout Vendor-defined additional information specific to the Primary Vendor Algorithm
NOTES: 1. Refer to Section 4.2.1 and Table 4 for the detailed definition of offset address as a function of device word width and mode. 2. BA = The beginning location of a Block Address (i.e., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table.
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28F160S3, 28F320S3
4.2.3 BLOCK STATUS REGISTER
The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations.
Block Erase Status (BSR.1) allows system software to determine the success of the last block erase operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation. This bit is only reset by issuing another erase operation to the block. The Block Status Register is accessed from word address 02h within each block.
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0000h or 0001h
Table 7. Block Status Register Offset Length (bytes) 01h Description 28F320S3/ 28F160S3 x16 Device/Mode BA+2:
(BA+2)h(1)
Block Status Register BSR.0 = Block Lock Status 1 = Locked 0 = Unlocked BSR.1 = Block Erase Status 1 = Last erase operation did not complete successfully 0 = Last erase operation completed successfully
BA+2 (bit 0): 0 or 1
BA+2 (bit 1): 0 or 1
BSR 2-7 Reserved for future use
BA+2 (bits 2-7): 0
NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.)
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4.2.4 Offset 10h 13h 15h 17h
28F160S3, 28F320S3
CFI QUERY IDENTIFICATION STRING
The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the specification and which vendor-specified command set(s) is (are) supported. Table 8. CFI Identification Length (Bytes) 03h Description Query-Unique ASCII string "QRY" 28F320S3/ 28F160S3 10: 11: 12: 13: 14: 15: 16: 17: 18: 19: 1A: 0051h 0052h 0059h 0001h 0000h 0031h 0000h 0000h 0000h 0000h 0000h
02h 02h 02h
Primary Vendor Command Set and Control Interface ID Code 16-bit ID Code for Vendor-Specified Algorithms Address for Primary Algorithm Extended Query Table Offset value = P = 31h Alternate Vendor Command Set and Control Interface ID Code Second Vendor-Specified Algorithm Supported Note: 0000h means none exists Address for Secondary Algorithm Extended Query Table Note: 0000h means none exists
19h
02h
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28F160S3, 28F320S3
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Table 9. System Interface Information Description VCC Logic Supply Minimum Program/Erase Voltage bits 7-4 BCD volts bits 3-0 BCD 100 mv VCC Logic Supply Maximum Program/Erase Voltage bits 7-4 BCD volts bits 3-0 BCD 100 mv VPP [Programming] Supply Minimum Program/Erase Voltage bits 7-4 HEX volts bits 3-0 BCD 100 mv VPP [Programming] Supply Maximum Program/Erase Voltage bits 7-4 HEX volts bits 3-0 BCD 100 mv Typical Time-Out per Single Byte/Word Program, 2N -sec Typical Time-Out for Max. Buffer Write, 2N -sec 2N m-sec 28F320S3/ 28F160S3 1B: 0030h 1C: 0055h 1D: 0030h
4.2.5
SYSTEM INTERFACE INFORMATION
The following device information can be useful in optimizing system interface software.
Offset 1Bh
Length (bytes) 01h
1Ch
01h
1Dh
01h
1Eh
01h
1E:
0055h
1Fh 20h 21h 22h 23h 24h 25h 26h
01h 01h 01h 01h 01h 01h 01h 01h
1F: 20: 21: 22: 23: 24: 25: 26:
0003h 0006h 000Ah 000Fh TBD TBD TBD TBD
Typical Time-Out per Individual Block Erase, Typical Time-Out for Full Chip Erase, 2N
m-sec
Maximum Time-Out for Byte/Word Program, 2N Times Typical Maximum Time-Out for Buffer Write, 2 N Times Typical Maximum Time-Out per Individual Block Erase, 2N Times Typical Maximum Time-Out for Chip Erase, 2N Times Typical
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4.2.6 DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. Table 10. Device Geometry Definition Offset 27h Length (bytes) 01h Description Device Size = 2N in Number of Bytes 28h 02h Flash Device Interface Description value 0002h 2Ah 2Ch 02h 01h meaning x8/x16 asynchronous
28F160S3, 28F320S3
28F320S3/ 28F160S3 27: 27: 28: 29: 0015h (16Mb) 0016h (32Mb) 0002h 0000h
Maximum Number of Bytes in Write Buffer = 2 N Number of Erase Block Regions within Device: bits 7-0 = x = # of Erase Block Regions
2A: 2B: 2C:
0005h 0000h 0001h
2Dh
04h
Erase Block Region Information bits 15-0 = y, Where y+1 = Number of Erase Blocks of Identical Size within Region bits 31-16 = z, Where the Erase Block(s) within This Region are (z) x 256 Bytes
y: 2D: 2E: y: 2D: 2E: z: 2F: 30:
32 Blk (16Mb) 001Fh 0000h 64 Blk (32Mb) 003Fh 0000h 64-KB 0000h 0001h
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28F160S3, 28F320S3
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Table 11. Primary-Vendor Specific Extended Query Description Primary Extended Query Table Unique ASCII String "PRI" Major Version Number, ASCII Minor Version Number, ASCII Optional Feature & Command Support bit 0 bit 1 bit 2 bit 3 bit 4 Chip Erase Supported Suspend Erase Supported Suspend Program Supported Lock/Unlock Supported Queued Erase Supported (1=yes, 0=no) (1=yes, 0=no) (1=yes, 0=no) (1=yes, 0=no) (1=yes, 0=no) 31: 32: 33: 34: 35: 36: 37: 38: 39: Data 0050h 0052h 0049h 0031h 0030h 000Fh 0000h 0000h 0000h
4.2.7
INTEL-SPECIFIC EXTENDED QUERY TABLE
Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information.
Offset(1) (P)h
Length (bytes) 03h
(P+3)h (P+4)h (P+5)h
01h 01h 04h
bits 5-31 Reserved for future use; undefined bits are "0"
(P+9)h 01h Supported Functions after Suspend Read Array, Status, and Query are always supported during suspended Erase or Program operation. This field defines other operations supported. bit 0 Program Supported after Erase Suspend (1=yes, 0=no) 3A: 0001h
bits 1-7 Reserved for future use; undefined bits are "0"
(P+A)h 02h Block Status Register Mask Defines which bits in the Block Status Register section of Query are implemented. bit 0 Block Status Register Lock-Bit [BSR.0] active (1=yes, 0=no) bit 1 Block Erase Status Bit [BSR.1] active (1=yes, 0=no) 3B: 3C: 0003h 0000h
bits 2-15 Reserved for future use; undefined bits are "0"
NOTES: 1. The variable P is a pointer which is defined at offset 15h in Table 8.
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Offset (P+C)h 01h (P+D)h 01h (P+E)h
28F160S3, 28F320S3
Table 11. Primary-Vendor Specific Extended Query (Continued) Description VCC Logic Supply Optimum Program/Erase voltage (highest performance) bits 7-4 bits 3-0 BCD value in volts BCD value in 100 mv 3E: 0050h 3D: Data 0050h
Length (bytes)
VPP [Programming] Supply Optimum Program/Erase voltage bits 7-4 bits 3-0 HEX value in volts BCD value in 100 mv
reserved
Reserved for future use
Table 12. Identifier Codes Code Manufacturer Code Device Code 16 Mbit 32 Mbit Block Lock Configuration * Block is Unlocked * Block is Locked * Reserved for Future Use Block Erase Status * Last erase completed successfully * Last erase did not complete successfully * Reserved for Future Use Address(2) 000000 000001 000001
X0002(1)
4.3
Data B0 D0 D4 DQ0 = 0 DQ0 = 1 DQ2-7
Read Identifier Codes Command
x0002(1) DQ1 = 0 DQ1 = 1
The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 6 retrieve the manufacturer, device, block lock configuration, and block erase status codes (see Table 12 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage. Following the Read Identifier Codes command, the information in Table 12 can be read.
4.4
DQ2-7
Read Status Register Command
NOTES: 1. X selects the specific block lock configuration code. See Figure 6 for the device identifier code memory map. 2. A0 should be ignored in this address. The lowest order address line is A1 in both word and byte mode.
The Status Register may be read to determine when programming, block erasure, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the Status Register until another valid command is written. The Status Register contents are latched on the falling edge of OE#, CE0#, or CE1# whichever occurs last. OE# or CEX# must toggle to VIH to update the Status Register latch. The Read Status Register command functions independently of the VPP voltage.
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28F160S3, 28F320S3
Following a program, block erase, set block lock-bit, or clear block lock-bits command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O pins DQ0-6 and DQ8-15 are invalid. When the operation completes or suspends (SR.7 = 1), all contents of the Status Register are valid when read. The eXtended Status Register (XSR) may be read to determine Write Buffer availability (see Table 16). The XSR may be read at any time by writing the Write to Buffer command. After writing this command, all subsequent read operations output data from the XSR, until another valid command is written. The contents of the XSR are latched on the falling edge of OE# or CEX# whichever occurs last in the read cycle. Write to buffer command must be re-issued to update the XSR latch.
analyzing STS in level RY/BY# mode or Status Register bit SR.7. Toggle OE#, CE0#, or CE1# to update the Status Register. When the block erase is complete, Status Register bit SR.5 should be checked. If a block erase error is detected, the Status Register should be cleared before system software attempts corrective actions. The CUI remains in read Status Register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both Status Register bits SR.4 and SR.5 being set to "1." Also, reliable block erasure can only occur when VCC = VCC1/2 and VPP = VPPH1/2. In the absence of these voltages, block contents are protected against erasure. If block erase is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1." Successful block erase requires that the corresponding block lock-bit be cleared, or WP# = VIH. If block erase is attempted when the corresponding block lock-bit is set and WP# = VIL, the block erase will fail and SR.1 and SR.5 will be set to "1."
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4.5
Clear Status Register Command
Status Register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 15). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or programming several bytes/words in sequence) may be performed. The Status Register may be polled to determine if an error occurred during the sequence. To clear the Status Register, the Clear Status Register command is written. It functions independently of the applied VPP voltage. This command is not functional during block erase or program suspend modes.
4.7
Full Chip Erase Command
4.6
Block Erase Command
The Full Chip Erase command followed by a Confirm command erases all unlocked blocks. After the Confirm command is written, the device erases all unlocked blocks from block 0 to block 31 (or 63) sequentially. Block preconditioning, erase, and verify are handled internally by the WSM. After the Full Chip Erase command sequence is written to the CUI, the device automatically outputs the Status Register data when read. The CPU can detect full chip erase completion by polling the STS pin in level RY/BY# mode or Status Register bit SR.7. When the full chip erase is complete, Status Register bit SR.5 should be checked to see if the operation completed successfully. If an erase error occurred, the Status Register should be cleared before issuing the next command. The CUI remains in read Status Register mode until a new command is issued. If an error is detected while erasing a block during a full chip erase operation, the WSM skips the remaining cells in that block and proceeds to erase the next block. Reading the block valid status code by issuing the Read Identifier Codes command or Query command informs the user of which block(s) failed to erase.
Block Erase is executed one block at a time and initiated by a two-cycle command. A Block Erase Setup command is written first, followed by a Confirm command. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs Status Register data when read (see Figure 10). The CPU can detect block erase completion by 26
ADVANCE INFORMATION
This two-step command sequence of setup followed by execution ensures that block contents are not accidentally erased. An invalid Full Chip Erase command sequence will result in both Status Register bits SR.4 and SR.5 being set to 1. Also, reliable full chip erasure can only occur when VCC = VCC1/2 and VPP = VPPH1/2. In the absence of these voltages, block contents are protected against erasure. If full chip erase is attempted while VPP VPPLK, SR.3 and SR.5 will be set to 1. When WP# = VIL, only unlocked blocks are erased. Full chip erase cannot be suspended.
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4.8
28F160S3, 28F320S3
If an error occurs while writing, the device will stop programming, and Status Register bit SR.4 will be set to a "1" to indicate a program failure. Any time a media failure occurs during a program or an erase (SR.4 or SR.5 is set), the device will not accept any more Write to Buffer commands. Additionally, if the user attempts to write past an erase block boundary with a Write to Buffer command, the device will abort programming. This will generate an "Invalid Command/Sequence" error and Status Register bits SR.5 and SR.4 will be set to "1." To clear SR.4 and/or SR.5, issue a Clear Status Register command. Reliable buffered programming can only occur when VCC = VCC1/2 and VPP = VPPH1/2. If programming is attempted while VPP VPPLK, Status Register bits SR.4 and SR.5 will be set to "1." Programming attempts with invalid VCC and VPP voltages produce spurious results and should not be attempted. Finally, successful programming requires that the corresponding Block Lock-Bit be cleared, or WP# = VIH. If a buffered write is attempted when the corresponding Block Lock-Bit is set and WP# = VIL, SR.1 and SR.4 will be set to "1."
Write to Buffer Command
To program the flash device via the write buffers, a Write to Buffer command sequence is initiated. A variable number of bytes or words, up to the buffer size, can be written into the buffer and programmed to the flash device. First, the Write to Buffer setup command is issued along with the Block Address. At this point, the eXtended Status Register information is loaded and XSR.7 reverts to the "buffer available" status. If XSR.7 = 0, no write buffer is available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a "1," the buffer is ready for loading. Now a Word/Byte count is issued at an address within the block. On the next write, a device start address is given along with the write buffer data. For maximum programming performance and lower power, align the start address at the beginning of a Write Buffer boundary. Subsequent writes must supply additional device addresses and data, depending on the count. All subsequent addresses must lie within the start address plus the count. After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM to begin copying the buffer data to the flash memory. If a command other than Write Confirm is written to the device, an "Invalid Command/Sequence" error will be generated and Status Register bits SR.5 and SR.4 will be set to "1." For additional buffer writes, issue another Write to Buffer setup command and check XSR.7. The write buffers can be loaded while the WSM is busy as long as XSR.7 indicates that a buffer is available. Refer to Figure 7 for the Write to Buffer flowchart.
4.9
Byte/Word Program Commands
Byte/Word programming is executed by a two-cycle command sequence. Byte/Word Program setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and verify algorithms internally. After the write sequence is written, the device automatically outputs Status Register data when read. The CPU can detect the completion of the program event by analyzing STS in level RY/BY# mode or Status Register bit SR.7. When programming is complete, Status Register bit SR.4 should be checked. If a programming error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. The CUI remains in read Status Register mode until it receives another command. Refer to Figure 8 for the Word/Byte Program flowchart. Also, Reliable byte/word programming can only occur when VCC = VCC1/2 and VPP = VPPH1/2. In the absence of this high voltage, contents are protected against programming. If a byte/word program is
ADVANCE INFORMATION
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28F160S3, 28F320S3
attempted while VPP VPPLK, Status Register bits SR.4 and SR.3 will be set to "1." Successful byte/word programming requires that the corresponding block lock-bit be cleared. If a byte/word program is attempted when the corresponding block lock-bit is set and WP# = VIL, SR.1 and SR.4 will be set to "1."
SR.7 can determine when the block erase operation has been suspended. When SR.7 = 1, SR.6 should also be set to "1," indicating that the device is in the erase suspend mode. STS in level RY/BY# mode will also transition to VOH. Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Program command sequence can also be issued during erase suspend to program data in other blocks. Using the Program Suspend command (see Section 4.12), a program operation can also be suspended. During a program operation with block erase suspended, Status Register bit SR.7 will return to "0" and STS in RY/BY# mode will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS in RY/BY# mode will return to VOL. After the Erase Resume command is written, the device automatically outputs Status Register data when read (see Figure 11). VPP must remain at VPPH1/2 and VCC must remain at VCC1/2 (the same VPP and VCC levels used for block erase) while block erase is suspended. RP# must also remain at VIH (the same RP# level used for block erase). Block erase cannot resume until program operations initiated during block erase suspend have completed.
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4.10
STS Configuration Command
The Status (STS) pin can be configured to different states using the STS pin Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued or RP# is low. Initially, the STS pin defaults to level RY/BY# operation where STS low indicates that the state machine is busy. STS high indicates that the state machine is ready for a new operation or suspended. To reconfigure the Status (STS) pin to other modes, the STS pin Configuration command is issued followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described in Table 14. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Write Complete interrupt pulse. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns. Supplying the 00h configuration code with the Configuration command resets the STS pin to the default RY/BY# level mode. Refer to Table 14 for configuration coding definitions. The Configuration command may only be given when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in both Status Register bits SR.4 and SR.5 being set to "1."
4.12
Program Suspend Command
4.11
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs Status Register data when read after the Block Erase Suspend command is written. Polling Status Register bit
The Program Suspend command allows program interruption to read data in other flash memory locations. Once the programming process starts, writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output Status Register data when read after the Program Suspend command is written. Polling Status Register bits SR.7 can determine when the programming operation has been suspended. When SR.7 = 1, SR.2 should also be set to "1", indicating that the device is in the program suspend mode. STS in level RY/BY# mode will also transition to VOH. Specification tWHRH1 defines the program suspend latency.
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ADVANCE INFORMATION
At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while programming is suspended are Read Status Register and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. Status Register bits SR.2 and SR.7 will automatically clear and STS in RY/BY# mode will return to VOL. After the Program Resume command is written, the device automatically outputs Status Register data when read. VPP must remain at VPPH1/2 and VCC must remain at VCC1/2 (the same VPP and VCC levels used for programming) while in program suspend mode. RP# must also remain at VIH (the same RP# level used for programming). Refer to Figure 9 for the Program Suspend/Resume flowchart.
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4.13
28F160S3, 28F320S3
A successful set block lock-bit operation requires that WP# = VIH. If it is attempted with WP# = VIL, the operation will fail and SR.1 and SR.4 will be set to "1." See Table 13 for write protection alternatives. Refer to Figure 12 for the Set Block Lock-Bit flowchart.
4.14
Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. This command is valid only when WP# = VIH. The clear block lock-bits operation is initiated using a two-cycle command sequence. A Clear Block Lock-Bits setup command is written followed by a Confirm command. Then, the device automatically outputs Status Register data when read (see Figure 13). The CPU can detect completion of the clear block lock-bits event by analyzing STS in level RY/BY# mode or Status Register bit SR.7. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in Status Register bits SR.4 and SR.5 being set to "1." Also, a reliable clear block lock-bits operation can only occur when VCC = VCC1/2 and VPP = VPPH1/2. If a clear block lock-bits operation is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1." In the absence of these voltages, the block lock-bits contents are protected against alteration. A successful clear block lock-bits operation requires that WP# = VIH. If a clear block lock-bits operation is aborted due to VPP or VCC transitioning out of valid range or RP# or WP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. When the operation is complete, Status Register bit SR.5 should be checked. If a clear block lock-bit error is detected, the Status Register should be cleared. The CUI will remain in read Status Register mode until another command is issued.
Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits. The block lock-bits gate program and erase operations. With WP# = VIH, individual block lock-bits can be set using the Set Block Lock-Bit command. Set block lock-bit is initiated using a two-cycle command sequence. The Set Block Lock-Bit setup along with appropriate block or device address is written followed by the Set Block Lock-Bit Confirm and an address within the block to be locked. The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs Status Register data when read. The CPU can detect the completion of the set lock-bit event by analyzing STS in level RY/BY# mode or Status Register bit SR.7. When the set lock-bit operation is complete, Status Register bit SR.4 should be checked. If an error is detected, the Status Register should be cleared. The CUI will remain in read Status Register mode until a new command is issued. This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in Status Register bits SR.4 and SR.5 being set to "1." Also, reliable operations occur only when VCC = VCC1/2 and VPP = VPPH1/2. In the absence of these voltages, lock-bit contents are protected against alteration.
ADVANCE INFORMATION
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28F160S3, 28F320S3
E
Table 13. Write Protection Alternatives WP# VIL or VIH VIL VIH Effect Block erase and programming enabled Block is locked. Block erase and programming disabled Block Lock-Bit override. Block erase and programming enabled All unlocked blocks are erased Block Lock-Bit override. All blocks are erased Set or clear block lock-bit disabled Set or clear block lock-bit enabled VIL VIH VIL VIH Table 14. Configuration Coding Definitions Reserved Pulse on Write Complete bit 1 DQ7-DQ2 are reserved for future use. default (DQ1/DQ0 = 00) RY/BY#, level mode ----used to control HOLD to a memory controller to prevent accessing a flash memory subsystem while any flash device's WSM is busy. configuration 01 ER INT, pulse mode(1) ----used to generate a system interrupt pulse when any flash device in an array has completed a block erase or sequence of queued block erases. Helpful for reformatting blocks after file system free space reclamation or `cleanup' configuration 10 PR INT, pulse mode(1) ----used to generate a system interrupt pulse when any flash device in an array has complete a program operation. Provides highest performance for servicing continuous buffer write operations. configuration ER/PR INT, pulse mode(1) ----used to generate system interrupts to trigger servicing of flash arrays when either erase or flash program operations are completed when a common interrupt service routine is desired. Pulse on Erase Complete bit 0
Operation Program and Block Erase
Block LockBit 0 1
Full Chip Erase
0,1 X
Set or Clear Block Lock-Bit
X
bits 7-2 DQ7-DQ2 = Reserved DQ1/DQ0 = STS Pin Configuration Codes 00 = default, level mode RY/BY# (device ready) indication 01 = pulse on Erase complete 10 = pulse on Flash Program complete 11 = pulse on Erase or Program Complete Configuration Codes 01b, 10b, and 11b are all pulse mode such that the STS pin pulses low then high when the operation indicated by the given configuration is completed. Configuration Command Sequences for STS pin configuration (masking bits D7-D2 to 00h) are as follows: Default RY/BY# level mode ER INT (Erase Interrupt): Pulse-on-Erase Complete PR INT (Program Interrupt): Pulse-on-Flash-Program Complete ER/PR INT (Erase or Program Interrupt): Pulse-on-Erase or Program Complete B8h, 00h B8h, 01h B8h, 02h B8h, 03h
NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
30
ADVANCE INFORMATION
E
Table 15. Status Register Definition WSMS 7 ESS 6 ECLBS 5 BWSLBS 4 VPPS 3 NOTES: SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block erase suspended 0 = Block erase in progress/completed SR.5 = ERASE AND CLEAR LOCK-BITS STATUS 1 = Error in block erasure or clear lock-bits 0 = Successful block erase or clear lock-bits SR.4 = PROGRAM AND SET LOCK-BIT STATUS 1 = Error in program or block lock-bit 0 = Successful program or set block lock-bit SR.3 = VPP STATUS 1 = VPP low detect, operation abort 0 = VPP OK BWSS 2
28F160S3, 28F320S3
DPS 1
R 0
Check STS in RY/BY# mode or SR.7 to determine block erase, programming, or lock-bit configuration completion. SR.6-0 are invalid while SR.7 = "0."
If both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered.
SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after a block erase, program, or lockbit configuration operation. SR.3 reports accurate feedback only when VPP = VPPH1/2.
SR.2 = PROGRAM SUSPEND STATUS 1 = Program suspended 0 = Program in progress/completed SR.1 = DEVICE PROTECT STATUS 1 = Block Lock-Bit and/or RP# lock detected, operation abort 0 = Unlock SR.1 does not provide a continuous indication of block lock-bit values. The WSM interrogates the block lock-bit, and WP# only after a block erase, program, or lock-bit configuration operation. It informs the system, depending on the attempted operation, if the block lock-bit is set. SR.0 is reserved for future use and should be masked when polling the Status Register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
Table 16. Extended Status Register Definition WBS 7 R 6 R 5 R 4 R 3 NOTES: XSR.7 = WRITE BUFFER STATUS 1 = Write to buffer available 0 = Write to buffer not available XSR.6 = RESERVED FOR FUTURE ENHANCEMENTS After a Write to buffer command, XSR.7 indicates that another Write to buffer command is possible. SR.6-0 are reserved for future use and should be masked when polling the status register 31 R 2 R 1 R 0
ADVANCE INFORMATION
28F160S3, 28F320S3
E
Command Bus Operation Write Write to Buffer Read
No
Start Set Time-Out Issue Write Command E8H, Block Address Read Extended Status Register Write Buffer Time-Out?
Comments
XSR.7 =
1
0
Write Word or Byte Count, Block Address Write Buffer Data, Start Address X=0
Yes
X=N
No
Yes
Abort Buffer Write Command?
Yes No
Yes
Write to Another Block Address Buffer Write to Flash Aborted
Data = E8h Addr = Block Address XSR.7=valid Addr = X Standby Check XSR.7 1 = Write buffer available 0 = Write buffer not available Write Data = N = word/byte count (Note 1, 2) N = 0 corresponds to count = 1 Addr = Block Address Write Data = write buffer data (Note 3, 4) Addr = device start address Write Data = write buffer data (Note 5, 6) Addr = device address Write Buffer Data = D0h write to flash Addr = X confirm Read Status Register data CE# & OE# low updates SR Addr = X Standby Check SR.7 1 = WSM ready 0 = WSM busy 1. Byte- or word-count values on DQ0-7 are loaded into the Count register. 2. The device now outputs the Status Register when read (XSR is no longer available). 3. Write Buffer contents will be programmed at the device start address or destination flash address. 4. Align the start address on a Write Buffer boundary for maximum programming performance. 5. The device aborts the Write to Buffer command if the current address is outside of the original block address. 6. The Status Register indicates an "improper command sequence" if the Write to Buffer command is aborted. Follow this with a Clear Status Register command. Full status check can be done after all Erase and Write sequences complete. Write FFh after the last operation to reset the device to Read Array mode.
Write Next Buffer Data, Device Address X=X+1 Buffer Write to Flash Confirm D0H Another Buffer Write?
No
Issue Read Status Command
Read Status Register
No
Suspend Write Loop Yes
SR.7 =
1
0
Suspend Write?
Full Status Check if Desired Buffer Write to Flash Complete
Figure 7. Write to Buffer Flowchart 32
ADVANCE INFORMATION
E
28F160S3, 28F320S3
Figure 8. Single Byte/Word Program Flowchart
ADVANCE INFORMATION
33
28F160S3, 28F320S3
E
Figure 9. Program Suspend/Resume Flowchart
34
ADVANCE INFORMATION
E
Start Device Supports Queuing
Yes
28F160S3, 28F320S3
Bus Command Comments Operation Write Erase Block Data = 28h or 20h Addr = Block Address XSR.7=valid Addr = X Standby Check XSR.7 1 = Erase queue available 0 = No Erase queue available Write Erase Block Data = 28H Addr = Block Address Read SR.7=valid; SR.6-0=X With the device enabled, OE# low updates SR Addr = X Standby Check XSR.7 1 = Erase queue available 0 = No Erase queue available Write Erase Data = D0H (Note 1) Confirm Addr = X Read Status Register data With the device enabled, OE# low updates SR Addr = X Standby Check SR.7 1 = WSM ready 0 = WSM busy 1. The Erase Confirm byte must follow Erase Setup when the Erase Queue status (XSR.7)=0. Full status check can be done after all Erase and Write sequences complete. Write FFh after the last operation to reset the device to Read Array mode. Read
Set Time-Out Issue Block Queue Erase Command 28H, Block Address
No
Read Extended Status Register Is Queue Available? XSR.7=
1=Yes
Erase Block Time-Out? Queued Erase Section (Include this section for compatibility with future SCS-compliant devices)
0=No
No
Yes
Another Block Erase?
Yes Yes
Issue Erase Command 28H Block Address
1=No No
Read Extended Status Register Is Queue Full? XSR.7=
0=Yes
Issue Single Block Erase Command 20H, Block Address Write Confirm D0H Block Address
Write Confirm D0H Block Address Another Block Erase?
No
Issue Read Status Command
Read Status Register
No Suspend Erase Loop
SR.7 =
1
0
Suspend Erase
Yes
Full Status Check if Desired Erase Flash Block(s) Complete
Figure 10. Block Erase Flowchart
ADVANCE INFORMATION
35
28F160S3, 28F320S3
E
Bus Operation Write Command Comments Erase Suspend Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed Erase Resume Data = D0H Addr = X Read Standby Standby Write Block Erase Completed
Start
Write B0H
Read Status Register
SR.7 =
0
1 0
SR.6 =
1 Read Read or Write? Write
Read Array Data
No Done? Yes Write D0H
Write Loop
Write FFH
Block Erase Resumed
Read Array Data
Figure 11. Block Erase Suspend/Resume Flowchart
36
ADVANCE INFORMATION
E
Start Bus Operation Write
Command
28F160S3, 28F320S3
Comments
Write 60H, Block/Device Address
Set Block/Master Lock-Bit Setup Set Block or Master Lock-Bit Confirm
Data = 60H Addr = Block Address (Block), Device Address (Master) Data = 01H (Block), F1H (Master) Addr = Block Address (Block), Device Address (Master) Status Register Data
Write 01H/F1H, Block/Device Address
Write
Read Status Register
Read
Standby 0 SR.7 =
Check SR.7 1 = WSM Ready 0 = WSM Busy
1 Full Status Check if Desired
Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode.
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Data (See Above)
Bus Operation
Command
Comments
SR.3 = 0
1
Standby
Voltage Range Error
Check SR.3 1 = Programming Voltage Error Detect Check SR.1 1 = Device Protect Detect RST# = VIH (Set Master Lock-Bit Operation) RST# = VIH , Master Lock-Bit Is Set (Set Block Lock-Bit Operation) Check SR.4,5 Both 1 = Command Sequence Error Check SR.4 1 = Set Lock-Bit Error
Standby SR.1 = 0 1 SR.4,5 = 0 1 SR.4 = 0 Set Lock-Bit Successful Set Lock-Bit Error Command Sequence Error 1
Device Protect Error
Standby
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery.
Figure 12. Set Block Lock-Bit Flowchart
ADVANCE INFORMATION
37
28F160S3, 28F320S3
E
Bus Operation Command Comments Write Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm Data = 60H Addr = X Data = D0H Addr = X Write
Read Status Register Data
Start
Write 60H
Write D0H
Read Status Register Standby 0 SR.7 = Write FFH after the Clear Block Lock-Bits operation to place device to read array mode. 1 Full Status Check if Desired Check SR.7 1 = WSM Ready 0 = WSM Busy
Clear Block Lock-Bits Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Data (See Above)
Bus Operation Standby
Command
Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.1 1 = Device Protect Detect RST# = VIH , Master Lock-Bit Is Set Check SR.4,5 Both 1 = Command Sequence Error
SR.3 = 0
1
Voltage Range Error Standby
SR.1= 0
1
Device Protect Error
Standby
1 SR.4,5 = 0 1 SR.5 = 0 Clear Block Lock-Bits Successful
Standby Command Sequence Error
Check SR.5 1 = Clear Block Lock-Bits Error
Clear Block Lock-Bits Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the Status Register before attempting retry or other error recovery.
Figure 13. Clear Block Lock-Bits Flowchart
38
ADVANCE INFORMATION
E
5.0 5.1 DESIGN CONSIDERATIONS Three-Line Output Control
Intel provides three control inputs to accommodate multiple memory connections: CEX# (CE0#, CE1#), OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation; b. Data bus contention avoidance. To use these control inputs efficiently, an address decoder should enable CEx# while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs, while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
28F160S3, 28F320S3
Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.
5.4
VPP Trace on Printed Circuit Boards
Updating target-system resident flash memories requires that the printed circuit board designer pay attention to VPP power supply traces. The VPP pin supplies the memory cell current for programming and block erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots.
5.5
VCC, VPP, RP# Transitions
5.2
STS and WSM Polling
STS is an open drain output that should be connected to VCC by a pull-up resistor to provide a hardware form of detecting block erase, program, and lock-bit configuration completion. In default mode, it transitions low during execution of these commands and returns to VOH when the WSM has finished executing the internal algorithm. For alternate STS pin configurations, see Section 4.10. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also VOH when the device is in block erase suspend (with programming inactive) or in reset/power-down mode.
Block erase, program, and lock-bit configuration are not guaranteed if RP# VIH, or if VPP or VCC fall outside of a valid voltage range (VCC1/2 and VPPH1/2). If VPP error is detected, Status Register bit SR.3 and SR.4 or SR.5 are set to "1." If RP# transitions to VIL during block erase, program, or lock-bit configuration, STS in level RY/BY# mode will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. Because the aborted operation may leave data partially altered, the command sequence must be repeated after normal operation is restored.
5.6
Power-Up/Down Protection
5.3
Power Supply Decoupling
The device offers protection against accidental block erase, programming, or lock-bit configuration during power transitions. A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CEX# must be low for a command write, driving either input signal to VIH will inhibit writes. The CUI's two-step command sequence architecture provides an added level of protection against data alteration. In-system block lock and unlock renders additional protection during power-up by prohibiting block erase and program operations. RP# = VIL disables the device regardless of its control inputs states. 39
Flash memory power switching characteristics require careful device decoupling. Standby current levels, active current levels and transient peaks produced by falling and rising edges of CEX# and OE# are areas of interest. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its VCC and GND and VPP and GND. These highfrequency, low-inductance capacitors should be placed as close as possible to package leads.
ADVANCE INFORMATION
28F160S3, 28F320S3
6.0 6.1
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
E
NOTICE: This datasheet contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design
Temperature under Bias ................ -40C to +85C Storage Temperature................... -65C to +125C Voltage On Any Pin (except VCC and VPP ) .................................... -0.5V to + VCC +0.5V(1) VCC Supply Voltage ............ -0.2V to + VCC+0.5V(1) VPP Update Voltage during Block Erase, Flash Write, and Lock-Bit Configuration ........... -0.2V to +7.0V(2) Output Short Circuit Current.....................100 mA(3)
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC and VPP pins. During transitions, this level may undershoot to -2.0V for periods <20 ns. Maximum DC voltage on input/output pins and VCC is VCC +0.5V which, during transitions, may overshoot to VCC +2.0V for periods <20 ns. 2. Maximum DC voltage on VPP may overshoot to +7.0V for periods <20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. 4. Operating temperature is for extended product defined by this specification.
6.2
Operating Conditions
Table 17. Temperature and VCC Operating Conditions(1)
Symbol TA VCC1 VCC2
Parameter Operating Temperature VCC Supply Voltage (2.7V to 3.6V) VCC Supply Voltage (3.3V 0.3V)
Notes
Min -40 2.7 3.0
Max +85 3.6 3.6
Unit C V V
Test Condition Ambient Temperature
NOTES: 1. Device operations in the VCC voltage ranges not covered in the table produce spurious results and should not be attempted.
40
ADVANCE INFORMATION
E
6.2.1 Symbol CIN COUT 6.2.2
28F160S3, 28F320S3
CAPACITANCE Table 18. Capacitance(1), TA = +25C, f = 1 MHz Parameter Input Capacitance Output Capacitance Typ 6 8 Max 8 12 Unit pF pF Condition VIN = 0.0V VOUT = 0.0V
NOTE: 1. Sampled, not 100% tested.
AC INPUT/OUTPUT TEST CONDITIONS
2.7 INPUT 0.0 1.35 TEST POINTS 1.35 OUTPUT
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for VCC = 2.7V-3.6V
3.0 INPUT 0.0 1.5 TEST POINTS 1.5 OUTPUT
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns.
Figure 15. Transient Input/Output Reference Waveform for VCC = 3.3V 0.3V (High Speed Testing Configuration)
1.3V 1N914
Test Configuration Capacitance Loading Value Test Configuration CL (pF) VCC = 3.3V 0.3V, 2.7V to 3.6V 50
R L = 3.3 k DEVICE UNDER TEST C L Includes Jig Capacitance OUT CL
Figure 16. Transient Equivalent Testing Load Circuit
ADVANCE INFORMATION
41
28F160S3, 28F320S3
6.2.3 Sym ILI ILO ICCS DC CHARACTERISTICS Table 19. DC Characteristics, TA = -40oC to +85oC Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 1,3,6 20 Typ Max 0.5 0.5 100 Unit A A A
E
Conditions
VCC = VCC1/2 Max VIN = VCC1/2 or GND VCC = VCC1/2 Max Vout = VCC1/2 or GND CMOS Inputs VCC = VCC1/2 Max CEX# = RP# = VCC 0.2V TTL Inputs VCC = VCC1/2 Max CEX# = RP# = VIH RP# = GND 0.2V IOUT (RY/BY#) = 0 mA CMOS Inputs VCC = VCC1/2 Max CEX# = GND f = 5 MHz, I OUT = 0 mA
0.2
2
mA
ICCD ICCR
VCC Deep Power-Down Current VCC Read Current
1 1,5,6
20 25
A mA
30
mA
TTL Inputs VCC = VCC1/2 Max CEX# = VIL f = 5 MHz, I OUT = 0 mA VPP = VPPH1/2 VPP = VPPH1/2 CEX# = VIH
ICCW ICCE
VCC Programming and Set Lock-Bit Current VCC Block Erase or Clear Block Lock-Bits Current
1,7 1,7 1,2 1
17 17 6
mA mA mA
ICCWS V Program Suspend or CC ICCES Block Erase Suspend Current IPPS IPPR IPPD IPPW IPPE IPPWS IPPES VPP Standby or VPP Read Current VPP Deep Power-Down Current VPP Program or Set Lock-Bit Current VPP Block Erase or Clear Block Lock-Bits Current VPP Program Suspend or Block Erase Suspend Current
1
2 10
15 200 5 80 40
A A A mA mA A
VPP VCC VPP VCC RP# = GND 0.2V VPP = VPPH1/2 VPP = VPPH1/2 VPP = VPPH1/2
1 1,7 1,7 1
0.1
10
200
42
ADVANCE INFORMATION
E
Sym VIL VIH VOL VOH1 VOH2 Parameter Input Low Voltage Input High Voltage Output Low Voltage VPPLK VPP Lockout Voltage VPPH1 VPP Voltage VPPH2 VPP Voltage VLKO
NOTES:
28F160S3, 28F320S3
Table 19. DC Characteristics (Continued) Notes Min Max Unit 7 7 3,7 3,7 3,7 2.4 0.85 x VCC VCC - 0.4 4,7 4 4 8 2.7 4.5 2.0 1.5 3.6 5.5 -0.5 2.0 0.8 VCC +0.5 0.4 V V V V V V V V V V VCC = VCC1/2 Min IOL = 5.8 mA VCC = VCC1/2 Min IOH = -2.5 mA VCC = VCC1/2 Min IOH = -2.5 mA VCC = VCC1/2 Min IOH = -100 A
Conditions
Output High Voltage (TTL) Output High Voltage (CMOS)
VCC Lockout Voltage
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25C. These currents are valid for all product versions (packages and speeds). 2. ICCWS and ICCES are specified with the device de-selected. If read or programmed while in erase suspend mode, the device's current is the sum of ICCWS or ICCES and ICCR or ICCW. 3. Includes STS in level RY/BY# mode. 4. Block erase, program, and lock-bit configurations are inhibited when VPP VPPLK, and not guaranteed in the ranges between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), and above VPPH2 (max). 5. Automatic Power Savings (APS) reduces typical ICCR to 3 mA at 2.7V and 3.3V VCC static operation. 6. CMOS inputs are either VCC 0.2V or GND 0.2V. TTL inputs are either VIL or VIH. 7. Sampled, not 100% tested. 8. With VCC VLKO flash memory writes are inhibited.
ADVANCE INFORMATION
43
28F160S3, 28F320S3
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS Table 20. AC Read Characteristics (1,5), TA = -40oC to +85oC Versions(4) (All units in ns unless otherwise noted) # Sym Parameter 16 Mbit 32 Mbit R2 tAVQV Address to Output Delay 16 Mbit 32 Mbit R3 tELQV CEX# to Output Delay 16 Mbit 32 Mbit R4 tGLQV OE# to Output Delay R5 tPHQV RP# High to Output Delay R6 tELQX CEX# to Output in Low Z R7 tGLQX OE# to Output in Low Z R8 tEHQZ CEX# High to Output in High Z R9 tGHQZ OE# High to Output in High Z R10 tOH Output Hold from Address, CEX#, or OE# Change, Whichever Occurs First 3 3 3 3 3 3 3 3 3 0 5 100 110 30 0 0 50 20 0 5 120 130 30 3.3V 0.3V VCC 2.7V - 3.6V VCC -100/-110 -120/-130
E
-130/-140 -150/-160 150 160 130 140 130 140 50 600 0 0 0 0 55 25 0 5 130 140 40 0 5 150 160 40 55 25 150 160 150 160 55 600
Notes Min Max Min Max Min Max Min Max 1 1 1 1 2 2 2 100 110 100 110 100 110 45 600 0 0 50 20 120 130 120 130 120 130 50 600 130 140
R1 tAVAV Read/Write Cycle Time
R11 tELFL CEX# Low to BYTE# High or Low tELFH R12 tFLQV BYTE# to Output Delay tFHQV 16 Mbit 32 Mbit R13 tFLQZ BYTE# to Output in High Z
NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX# without impact on tELQV. 3. Sampled, not 100% tested. 4. See Ordering Information for device speeds (valid operational combinations). 5. See Figures 14 through 16 for testing characteristics.
44
ADVANCE INFORMATION
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28F160S3, 28F320S3
Note: CEX# is the latter of CE0# and CE1# low or the first of CE0# or CE1# high.
Figure 17. AC Waveform for Read Operations
ADVANCE INFORMATION
45
28F160S3, 28F320S3
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS Table 21. Write Operations(1,5,6), TA = -40C to +85C Versions(5) # W1 W2 Sym tPHWL (tPHEL) tELWL (tWLEL) W3 tWLWH (tELEH) W4 W5 W6 Parameter RP# High Recovery to WE# (CEX#) Going Low CEX# Setup to WE# Going Low (WE# Setup to CEX# Going Low) WE# Pulse Width (CEX# Pulse Width) 3 3 3.3V 0.3V, 2.7V-3.6V VCC Notes 2
E
Valid for All Speeds Min 1 10 0 50 70 50 50 10 0 5 5 30 25 100 Max Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 ns ns ns
tDVWH (tDVEH) Data Setup to WE# (CEX# ) Going High tAVWH (tAVEH) tWHEH (tEHWH) Address Setup to WE# (CEX# ) Going High CEX# Hold from WE# High (WE# Hold from CEX# High)
W7 W8 W9
tWHDX (tEHDX) Data Hold from WE# (CEX# ) High tWHAX (tEHAX) tWHWL (tEHEL) Address Hold from WE# (CEX# ) High WE# Pulse Width High (CEX# Pulse Width High)
W10 W11 W12 W13 W14 W15
tSHWH (tSHEH) WP# VIH Setup to WE# (CEX# ) Going High tVPWH (tVPEH) VPP Setup to WE# (CEX# ) Going High 2
100 0
tWHGL (tEHGL) Write Recovery before Read tWHRL (tEHRL) tQVSL tQVVL WE# High to STS in RY/BY# Low WP# VIH Hold from Valid SRD VPP Hold from Valid SRD, STS in RY/BY# High 2,4 2,4
0 0
NOTES: 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN and DIN for block erase, program, or lock-bit configuration. 4. VPP should be at VPPH1/2 until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Ordering Information for device speeds (valid operational combinations). 6. See Figures 14 through 16 for testing characteristics.
46
ADVANCE INFORMATION
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28F160S3, 28F320S3
NOTES: A. VCC power-up and standby. B. Write block erase or program setup. C. Write block erase confirm or valid address and data.. D. Automated erase or program delay. E. Read Status Register data. F. Write Read Array command. CEX# is the latter of CE0# and CE1# low or the first of CE0# or CE1# high.
Figure 18. AC Waveform for Write Operations
ADVANCE INFORMATION
47
28F160S3, 28F320S3
6.2.6 RESET OPERATIONS
E
Figure 19. AC Waveform for Reset Operation
Table 22. Reset AC Specifications(1) VCC = 2.7V # P1 Sym tPLPH Parameter RP# Pulse Low Time (If RP# is tied to V CC, this specification is not applicable) RP# Low to Reset during Block Erase, Program, or Lock-Bit Configuration VCC at 2.7V to RP# High VCC at 3.0V to RP# High 2,3 Notes Min 100 Max VCC = 3.3V Min 100 Max Unit ns
P2 P3
tPLRH t3VPH
20 50
20 50
s s
NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing, the reset will complete within tPLPH. 3. A reset time, tPHQV, is required from the latter of STS in RY/BY# mode or RP# going high until outputs are valid.
48
ADVANCE INFORMATION
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6.2.7 # W16 W16 W16 W16 W16 W16 W16 W16 Sym
28F160S3, 28F320S3
ERASE, PROGRAM, AND LOCK-BIT CONFIGURATION PERFORMANCE Table 23. Erase/Write/Lock Performance(3,4) 2.7V-3.6V VCC Version Parameter Byte/word program time (using write buffer) Notes 5 2 2 2 2 2 2 2.7V VPP Typ(1) 5.76 19.89 22.17 1.63 0.91 0.37 0.56 17.9 35.8 2 2 22.17 0.56 7.24 15.5 TBD TBD 10.2 21.5 Max TBD TBD TBD TBD TBD TBD TBD 3.3V VPP Typ(1) 5.76 19.89 22.17 1.63 0.91 0.37 0.56 17.9 35.8 22.17 0.56 7.24 15.5 TBD TBD 10.2 21.5 Max TBD TBD TBD TBD TBD TBD TBD 5V VPP Typ(1) 2.76 13.2 13.2 0.87 0.44 0.16 0.42 13.3 26.6 13.3 0.42 6.73 TBD TBD 9.48 Max TBD TBD TBD TBD TBD TBD TBD Units s s s sec sec sec sec sec sec s sec s s
tWHQV1 Per byte program time tEHQV1 (without write buffer) tWHQV1 Per word program time tEHQV1 (without write buffer) Block program time (byte mode) Block program time (word mode) Block program time (using write buffer) tWHQV2 Block erase time tEHQV2 Full chip erase time 16 Mbit 32 Mbit
tWHQV3 Set Lock-Bit time W16 tEHQV3 tWHQV4 Clear block lock-bits time W16 tEHQV4 tWHRH1 Program suspend latency W16 tEHRH1 time to read tWHRH2 Erase suspend latency time W16 tEHRH2 to read
12.54 17.54
NOTES: 1. Typical values measured at TA = +25C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled but not 100% tested. 5. Uses whole buffer.
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28F160S3, 28F320S3
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Table 24. Erase/Write/Lock Performance(3,4) 3.3V 0.3V VCC 3.3V VPP Notes 5 2 2 2 2 2 2 16 Mbit 32 Mbit Typ(1) 5.66 19.51 21.75 1.6 0.89 0.36 0.55 17.6 35.2 2 2 22.75 0.55 7.1 15.2 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 10 21.1 5V VPP Typ(1) 2.7 12.95 12.95 0.85 0.43 0.18 0.41 13.1 26.2 12.95 0.41 6.6 12.3 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 9.3 17.2 Units s s s sec sec sec sec sec sec s sec s s Parameter
Version # W16 tWHQV1 W16 tEHQV1 tWHQV1 W16 tEHQV1 W16 W16 W16 tWHQV2 W16 tEHQV2 W16 Sym
Byte/word program time (using write buffer) Per byte program time (without write buffer) Per word program time (without write buffer) Block program time (byte mode) Block program time (word mode) Block program time (using write buffer) Block erase time Full chip erase time
tWHQV3 W16 tEHQV3 tWHQV4 W16 tEHQV4 tWHRH1 W16 tEHRH1 tWHRH2 W16 tEHRH2
Set Lock-Bit time Clear block lock-bits time Program suspend latency time to read Erase suspend latency time to read
NOTES: 1. Typical values measured at TA = +25C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled but not 100% tested. 5. Uses whole buffer.
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E
28F160S3, 28F320S3
APPENDIX A DEVICE NOMENCLATURE AND ORDERING INFORMATION
Product line designator for all Intel Flash products
T E 2 8 F 1 6 0 S3 - 1 0 0
Package DT = Extended Temp. 56-Lead SSOP TE = Extended Temp. 56-Lead TSOP GT = Extended Temp. 56-Bump BGA* package Device Density 160 = 16-Mbit 320 = 32-Mbit
Access Speed (ns) 100 ns (3.3V), 120 ns (2.7V-3.6V)
Device Type 3 = 2.7V / 3.3V VCC 2.7V/3.3V / 5V VPP Product Family S = FlashFileTM Memory
Order Code by Density 16 Mb 56-lead TSOP S3-100 56-lead TSOP S3-130 56-lead SSOP S3-100 56-lead SSOP S3-130 56-bump BGA S3-100 56-bump BGA S3-130 32 Mb 56-lead TSOP S3-110 56-lead TSOP S3-140 56-lead SSOP S3-110 56-lead SSOP S3-140 56-bump BGA S3-110 56-bump BGA S3-140
Valid Operational Combinations 2.7V-3.6V VCC 50 pF load (16 Mb / 32 Mb) -120 / -130 -150 / -160 -120 / -130 -150 / -160 -120 / -130 -150 / -160 3.3V 0.3V VCC 50 pF load (16 Mb / 32 Mb) -100 / -110 -130 / -140 -100 / -110 -130 / -140 -100 / -110 -130 / -140
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28F160S3, 28F320S3
APPENDIX B ADDITIONAL INFORMATION(1,2)
Order Number 290609 292203 292204 www.mcif.com 290528 290489 297372 292123 292144 292159 292163 Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office Document/Tool
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Word-Wide FlashFile MemoryTM Family 28F160S5, 28F320S5 Datasheet AP-645 28F160S3/S5 Compatibility with 28F016SA/SV AP-646 Common Flash Interface (CFI) and Command Sets Common Flash Interface Specification 28F016SV 16-Mb (1Mbit x 16, 2 Mbit x 8) FlashFileTM Memory Datasheet 28F016SA 16-Mb (1Mbit x 16, 2 Mbit x 8) FlashFileTM Memory Datasheet 16-Mbit Flash Product Family User's Manual AP-374 Flash Memory Write Protection Techniques AP-393 28F016SV Compatibility with 28F016SA AP-607 Multi-Site Layout Planning with Intel's FlashFileTM Components, Including ROM Capability AP-610 Flash Memory In-System Code and Data Update Techniques Mechanical Specification BGA* Package Preliminary Guide Surface Mount and PCB Guidelines for BGA* Packaging Multi-Site Layouts: 56-lead TSOP to 56-bump BGA* package 56-lead SSOP to 56-bump BGA package CFI - Common Flash Interface Reference Code
NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools.
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